logo

Standards Manage Your Business

We Manage Your Standards

IEC

IEC 62530:2021

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Standard Details

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

General Information

Status : ACTIVE
Standard Type: Main
Document No: IEC 62530:2021
Document Year: 2021
Pages: 1315
Edition: 3.0
  • Section Volume:
  • TC 91 Electronics assembly technology
  • ICS:
  • 25.040.01 Industrial automation systems in general
  • 35.060 Languages used in information technology

Life Cycle

Currently Viewing

ACTIVE
IEC 62530:2021
Knowledge Corner

Expand Your Knowledge and Unlock Your Learning Potential - Your One-Stop Source for Information!

© Copyright 2024 BSB Edge Private Limited.

Enquire now +