logo

Standards Manage Your Business

We Manage Your Standards

IEC

IEC 62530:2011

SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Standard Details

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both StandardDetails were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog StandardDetails, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

General Information

Status : WITHDRAWN
Standard Type: Main
Document No: IEC 62530:2011
Document Year: 2011
Pages: 1251
Edition: 2.0
  • Section Volume:
  • TC 91 Electronics assembly technology
  • ICS:
  • 25.040.01 Industrial automation systems in general

Life Cycle

Currently Viewing

WITHDRAWN
IEC 62530:2011
Knowledge Corner

Expand Your Knowledge and Unlock Your Learning Potential - Your One-Stop Source for Information!

© Copyright 2024 BSB Edge Private Limited.

Enquire now +