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IEC 62530:2007

Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Standard Details

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

General Information

Status : WITHDRAWN
Standard Type: Main
Document No: IEC 62530:2007
Document Year: 2007
Pages: 663
Edition: 1.0
  • Section Volume:
  • TC 91 Electronics assembly technology
  • ICS:
  • 25.040.01 Industrial automation systems in general

Life Cycle

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IEC 62530:2007
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