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IEC 62530-2 : 2023

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

Standard Details

IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.

General Information

Status : ACTIVE
Standard Type: Main
Document No: IEC 62530-2 : 2023
Document Year: 2023
Pages: 457
Edition: 2.0
  • Section Volume:
  • TC 91 Electronics assembly technology
  • ICS:
  • 25.040.01 Industrial automation systems in general
  • 35.060 Languages used in information technology

Life Cycle

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ACTIVE
IEC 62530-2 : 2023
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